
W9816G6IH
10.4 Mode Register Set Cycle
t RSC
CLK
CS
RAS
CAS
WE
A0-A10
BA
t CMS
t CMS
t CMS
t CMS
t AS
t CMH
t CMH
t CMH
t CMH
t AH
Register
set data
next
A0
Reserved
A0
A1
A2
A3
A4
A5
Burst Length
Addressing Mode
CAS Latency
command
A1
A0
A2 A0
1
1
1
1
0 A0
0 A0
0 A0
0 A0
1 A0
1 A0
1 A0
1 A0
A0
0
1
0
1
0
1
0
1
A0
Burst Length
A0 A0
Sequential Interleave
1
2 2
4 4
8 8
1 A0
A0 A0
A0 A0
A0 A0
A0
A0
Reserved
Full Page
A7
A6
A0
"0"
(Test Mode)
A3
1
A0
A0
A0
A0
Addressing Mode
A0
A0
Sequential
Interleave
A9
A8
A0
A10
A0
BA
"0"
"0"
"0"
Reserved
Write A0 Mode
Reserved
A6
0
0
0
0
1
A5
1
1
A0
A0
A0
A0
A0
A0
A4
0
1
0
1
0
A0
CAS Latency
A0
A0
Reserved
Reserved
2
3
A0
Reserved
- 20 -
A0
1
A9
A0
A0
Single Write Mode
A0
A0
Burst read and Burst write
Burst read and single write
Publication Release Date: Mar. 22, 2010
Revision A02